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Experiences

  • R&D Software Engineer, Front End Group, Cadence Design Systems, San Jose, CA. July 2010 - Present.
  • R&D Software Engineer, Test Synthesis Group, Silicon Test Solutions Center at Mentor Graphics Corp., Wilsonville, OR. March 2009 - July 2010.
  • Cognitive Engine (CE) with Case base Reasoning (CBR), CWT lab, Virginia Tech. 2008.5 – 2008.12.
  • Smart Radio Challenger for SDR Forum 2008, Virginia Tech, 2007.10 – 2008.10.
  • Tools to convert CNF into pseudo circuit. Proactive Lab, Virginia Tech. 2008.1 – 2008.8.
  • Public Safety Cognitive Radio, CWT lab, EE Dept. of Virginia Tech. 2007.01-2008.05.
  • Efficient Power Droop Aware Delay Fault Testing, Proactive Lab, Virginia Tech, 2006 – 2007.
  • All Solution SAT Solver, Proactive Lab, Virginia Tech, 2003-2004.
  • COURSE PROJECTS FOR TESTING & VERIFICATION, Proactive Lab, Virginia Tech, 2002-2003
    • SAT Solver.
    • PODEM Based ATPG Solver.
    • CNF Implication graph Tool.
    • Circuit Gate Level Simulator.
  • Proactive Lab Website, Proactive Lab, Virginia Tech, 2002.9.
  • Housing Rent Web Site, Off Campus Housing Office, Virginia Tech, 2002.5-2002.8.
  • War Memorial Chapel Website, UUSA, Virginia Tech, 2002.5-2002.8.
  • SNAPSTER Distribute File System, CS Dept, Virginia Tech, 2001.9-2001.12
  • Network Visual Classroom System, CS Dept, Virginia Tech, 2001.9-2001.12

Others experiences before visit United States:

  • An Automatic Test System for Testing Parameters of the SCR-DC Motor. Wuhan Automotive Polytechnic University. 2000.
  • Research Assistant, Control Theory & Engineering Laboratory, Huazhong Univ. of Science & Technology, Sept. 1999-June. 2000.
  • Designed security electronic defrayal network system smart IC card POS device.
  • Designed the security model for authorities and data communication
  • Programmer, Shenzhen Science Association
  • Designed and implemented Universe Multimedia Museum.
  • Designed and implemented 3D animation using 3ds max etc.
  • Co-op Programmer, Wuhan CCTV, P.R.C.
  • Designed and implemented Advertisement MIS
  • Research Assistant, Electronics Research Laboratory, Huazhong Univ. of Science & Technology
  • Optimized patch clamp amplifiers circuit layout.
  • Implemented patch clamp amplifiers prototype and verified element parameters.
  • Designed AD/DA control & sampler card.
  • Designed and implemented control/driver software.